A device structure for a superjunction insulated-gate bipolar transistor featuring a floating charge-carrier accumulation layer has been proposed and investigated via computer simulation. In this structure, the accumulation layer is shielded by an underlying p-type layer. It is established that the charge-carrier concentration within the accumulation layer does not affect the breakdown voltage. Furthermore, the proposed insulated-gate bipolar transistor structure demonstrates superior efficiency compared to conventional superjunction trench insulated-gate bipolar transistor’s, as well as those utilizing a floating p-region or an adaptive holeextraction path. Specifically, at an identical on-state voltage drop of 0.946 V, the turn-off energy loss of the proposed device is 75.38 % lower than that of a superjunction trench insulated-gate bipolar transistor with a floating p-region, and 52 % lower than that of a device with an adaptive hole-extraction path. Conversely, for a constant turn-off energy loss of 2.3 mJ/cm², the on-state voltage drop of the proposed device is 39.86 % lower than that of a standard superjunction trench insulated-gate bipolar transistor.

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