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<article article-type="research-article" dtd-version="1.3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:lang="ru"><front><journal-meta><journal-id journal-id-type="publisher-id">bsuir</journal-id><journal-title-group><journal-title xml:lang="ru">Доклады БГУИР</journal-title><trans-title-group xml:lang="en"><trans-title>Doklady BGUIR</trans-title></trans-title-group></journal-title-group><issn pub-type="ppub">1729-7648</issn><issn pub-type="epub">2708-0382</issn><publisher><publisher-name>БГУИР</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.35596/1729-7648-2026-24-5-24-32</article-id><article-id custom-type="elpub" pub-id-type="custom">bsuir-4444</article-id><article-categories><subj-group subj-group-type="heading"><subject>Research Article</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="ru"><subject>Статьи</subject></subj-group></article-categories><title-group><article-title>Суперпереходный биполярный транзистор с изолированным затвором и вертикальным рас­ положением канала с экранированным плавающим слоем накопления носителей заряд</article-title><trans-title-group xml:lang="en"><trans-title>Super-Junction Insulated-Gate Bipolar Transistor with a Vertical Channel Arrangement and a Shielded Floating Charge-Carrier Accumulation Layer</trans-title></trans-title-group></title-group><contrib-group><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Чонг</surname><given-names>Тхань Нгуен</given-names></name><name name-style="western" xml:lang="en"><surname>Trong</surname><given-names>Thanh Nguyen</given-names></name></name-alternatives><bio xml:lang="ru"><p>Чонг Тхань Нгуен, асп. каф. микрои наноэлектроники</p><p>Минск</p></bio><bio xml:lang="en"><p>Trong Thanh Nguyen, Postgraduate of the Department of Microand Nanoelectronics</p><p>Minsk</p></bio><xref ref-type="aff" rid="aff-1"/></contrib><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Ловшенко</surname><given-names>И. Ю.</given-names></name><name name-style="western" xml:lang="en"><surname>Lovshenko</surname><given-names>I.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Ловшенко И. Ю., зав. науч.-исслед. лаб. «Компьютерное проектирование микрои наноэлектронных систем» (НИЛ 4.4)</p><p>Минск</p></bio><bio xml:lang="en"><p>Lovshenko I., Head of the Research Laboratory “Computer-Aided Design of Microand Nanoelectronic Systems” (Lab. 4.4)</p><p>Minsk</p></bio><xref ref-type="aff" rid="aff-1"/></contrib><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Волчёк</surname><given-names>В. С.</given-names></name><name name-style="western" xml:lang="en"><surname>Volcheck</surname><given-names>V.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Волчёк Владислав Сергеевич, канд. техн. наук, ст. науч. сотр. НИЛ 4.4 Тел.: +375 17 293-86-79</p><p>220013, Минск, ул. П. Бровки, 6</p></bio><bio xml:lang="en"><p> Volcheck Vladislav, Cand. Sci. (Tech.), Senior Researcher at the Lab. 4.4  Tel.: +375 17 293-86-79</p><p>220013, Minsk, P. Brovki St., 6</p></bio><email xlink:type="simple">vlad.volchek@bsuir.by</email><xref ref-type="aff" rid="aff-1"/></contrib><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Новиков</surname><given-names>П. Э.</given-names></name><name name-style="western" xml:lang="en"><surname>Novikov</surname><given-names>P.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Новиков П. Э., мл. науч. сотр. НИЛ 4.4</p><p>Минск</p></bio><bio xml:lang="en"><p>Novikov P., Junior Research at the Lab. 4.4</p><p>Minsk</p></bio><xref ref-type="aff" rid="aff-1"/></contrib><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Стемпицкий</surname><given-names>В. Р.</given-names></name><name name-style="western" xml:lang="en"><surname>Stempitsky</surname><given-names>V.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Стемпицкий В. Р., канд. техн. наук, доц., науч. рук. НИЛ 4.4, проректор по научной работе</p><p>Минск</p></bio><bio xml:lang="en"><p>Stempitsky V., Cand. Sci. (Tech.), Associate Professor, Scientific Director of the Lab. 4.4, Vice-Rector for Research</p><p>Minsk</p></bio><xref ref-type="aff" rid="aff-1"/></contrib></contrib-group><aff-alternatives id="aff-1"><aff xml:lang="ru"><institution>Белорусский государственный университет информатики и радиоэлектроники</institution><country>Беларусь</country></aff><aff xml:lang="en"><institution>Belarusian State University of Informatics and Radioelectronics</institution><country>Belarus</country></aff></aff-alternatives><pub-date pub-type="collection"><year>2026</year></pub-date><pub-date pub-type="epub"><day>07</day><month>11</month><year>2026</year></pub-date><volume>24</volume><issue>5</issue><fpage>24</fpage><lpage>32</lpage><permissions><copyright-statement>Copyright &amp;#x00A9; Чонг Т., Ловшенко И.Ю., Волчёк В.С., Новиков П.Э., Стемпицкий В.Р., 2026</copyright-statement><copyright-year>2026</copyright-year><copyright-holder xml:lang="ru">Чонг Т., Ловшенко И.Ю., Волчёк В.С., Новиков П.Э., Стемпицкий В.Р.</copyright-holder><copyright-holder xml:lang="en">Trong T., Lovshenko I., Volcheck V., Novikov P., Stempitsky V.</copyright-holder><license xml:lang="ru" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>Данная работа распространяется под лицензией Creative Commons Attribution 4.0.</license-p></license><license xml:lang="en" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>This work is licensed under a Creative Commons Attribution 4.0 License.</license-p></license></permissions><self-uri xlink:href="https://doklady.bsuir.by/jour/article/view/4444">https://doklady.bsuir.by/jour/article/view/4444</self-uri><abstract><p>Предложена и исследована посредством компьютерного моделирования приборная структура суперпереходного биполярного транзистора с изолированным затвором с плавающим слоем накопления носителей заряда. В рассматриваемой структуре слой накопления экранируется расположенным под ним p-слоем. Установлено, что концентрация в слое накопления носителей заряда не влияет на напряжение пробоя, а предлагаемая приборная структура биполярного транзистора с изолированным затвором обладает более высокой эффективностью по сравнению с традиционным суперпереходным траншейным биполярным транзистором с изолированным затвором, суперпереходными траншейными биполярными транзисторами с изолированным затвором с плавающей p-областью и с адаптивным путем экстракции дырок. Так, при одинаковом падении напряжения в открытом состоянии 0,946 В энергия потерь при выключении у предлагаемого прибора на 75,38 % меньше, чем у суперпереходного траншейного биполярного транзистора с изолированным затвором с плавающей p-областью, и на 52 % меньше, чем у транзистора с адаптивным путем экстракции дырок. При одинаковой энергии потерь при выключении 2,3 мДж/см2 падение напряжения в открытом состоянии у предлагаемого прибора на 39,86 % меньше, чем у суперпереходного траншейного биполярного транзистора с изолированным затвором.</p></abstract><trans-abstract xml:lang="en"><p>A device structure for a superjunction insulated-gate bipolar transistor featuring a floating charge-carrier accumulation layer has been proposed and investigated via computer simulation. In this structure, the accumulation layer is shielded by an underlying p-type layer. It is established that the charge-carrier concentration within the accumulation layer does not affect the breakdown voltage. Furthermore, the proposed insulated-gate bipolar transistor structure demonstrates superior efficiency compared to conventional superjunction trench insulated-gate bipolar transistor’s, as well as those utilizing a floating p-region or an adaptive holeextraction path. Specifically, at an identical on-state voltage drop of 0.946 V, the turn-off energy loss of the proposed device is 75.38 % lower than that of a superjunction trench insulated-gate bipolar transistor with a floating p-region, and 52 % lower than that of a device with an adaptive hole-extraction path. Conversely, for a constant turn-off energy loss of 2.3 mJ/cm2, the on-state voltage drop of the proposed device is 39.86 % lower than that of a standard superjunction trench insulated-gate bipolar transistor.</p></trans-abstract><kwd-group xml:lang="ru"><kwd>баланс заряда</kwd><kwd>моделирование</kwd><kwd>напряжение пробоя</kwd><kwd>падение напряжения в открытом состоянии</kwd><kwd>силовая электроника</kwd><kwd>слой накопления носителей заряда</kwd><kwd>суперпереходный биполярный транзистор с изолированным затвором</kwd><kwd>транзистор траншейного типа</kwd><kwd>экранирующий плавающий слой</kwd><kwd>энергия потерь</kwd></kwd-group><kwd-group xml:lang="en"><kwd>charge balance</kwd><kwd>modeling</kwd><kwd>breakdown voltage</kwd><kwd>on-state voltage drop</kwd><kwd>power electronics</kwd><kwd>charge-carrier accumulation layer</kwd><kwd>superjunction insulated-gate bipolar transistor</kwd><kwd>trench-gate transistor</kwd><kwd>floating shielding layer</kwd><kwd>energy loss</kwd></kwd-group></article-meta></front><back><ref-list><title>References</title><ref id="cit1"><label>1</label><citation-alternatives><mixed-citation xml:lang="ru">Iwamuro N., Laska T. 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